Apolonij Rodoški v katulovi 64. pesmi

فهرست مقالات شماره 64

A Voltage Scalable 0 . 26 V , 64 kb 8 T SRAM With V � Lowering Techniques and Deep Sleep Mode

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a re...

64 - bit CPUs : UltraSPARC - III vs . Intel IA - 64

This communication sets an evaluation framework and performs a comparative analysis of the UltraSPARC-III and the IA-64 processor architectures. It starts with an overview of a pure RISC architecture and the new EPIC technology. It then presents the unique combination of innovative features that both manufacturers claim explicit parallelism, predication and speculative loading – and the goals f...

Input ( 64 x 64 ) Motion Energy X Velocity Integration

Neurons in area MT of primate visual cortex encode the velocity of moving objects. We present a model of how MT cells aggregate responses from V1 to form such a velocity representation. Two diierent sets of units, with local receptive elds, receive inputs from motion energy lters. One set of units forms estimates of local motion, while the second set computes the utility of these estimates. Out...

SPIM : A Pipelined 64 X 64 - bit Iterative Multiplier

A 64 X64-bit iterating multiplier, the Stanford Pipelined Iterative Multiplier (SPIM), is presented. Tbe pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a Wallace tree for a VLSI implementation because it is a more regular structure. A 4:2 carry-save accumulator at the bottom of the array is used to iteratively accumulate partial products, allowing a p...